1. Field of the Invention
The invention relates to the field of data processing systems. More particularly, this invention relates to programmable data processing systems in which an instruction decoder is responsive to program instructions to control processing logic to perform data processing operations specified by computer program instructions.
2. Description of the Prior Art
It is known to provide data processing systems that support more than one instruction set. Examples of such data processing systems are the processor cores designed by ARM Limited of Cambridge, England. ARM processors typically support two instruction sets: the ARM instruction set in which all instructions are 32-bits long; and a Thumb instruction set that compresses the most commonly used instructions into a 16-bit format. ARM Jazelle processors include a third instruction set—Java bytecodes and can easily switch between a Java state in which Java bytecodes are treated as native instructions and the ARM/Thumb state. It is difficult to produce an efficient highly pipelined processor that is able to execute Java bytecodes as native instructions.
An alternative approach is that bytecodes are translated into native ARM/Thumb instructions by a Just In Time (JIT) compiler or a dynamic adaptive compiler. Such translators often produce code that is considerably larger in size that the original non-native bytecodes thus requiring a disadvantageously increased amount of storage space.
It is known to provide a single instruction in which a comparison and a branch that switches program execution from one point to another are combined. Such known compare and branch instructions calculate a target branch point using a field within the instruction itself. This is done, for example, by specifying a 16-bit offset in a field of the instruction and by computing the target branch address from the offset relative to the memory address of the branch instruction itself. For a fixed-size instruction of say 32-bits, the number of bits available to specify the target branch point is limited. The lack of flexibility in the range of target branch addresses that may be specified within the instruction is particularly disadvantageous when dealing with unplanned changes in the flow of control of the program such, as when an exception occurs, or in the case of branch instructions to long-range subroutine calls.